The present invention relates to a serial transmission path switching system for selectively switching and connecting communication devices having a plurality of transfer rates.
Along with the recent advance in the digital technology, digitalization of HDTV signals is realized as well as that of conventional standard TV signals. Digitalization of video signals is also prompting development of video compression techniques such as MPEG or JPEG. For example, a broadcasting station uses video signals with various transfer rates. Examples of the video signals with different transfer rates are an HDTV baseband signal (1.5 Gbps), a standard TV signal (143 Mbps, 177 Mbps, 270 Mbps, 360 Mbps, 540 Mbps, or the like), and a compressed video signal (MPEG, JPEG, or the like). In this specification, a “video signal” means a signal containing not only image information but also an audio component and sync signals.
In this case, a serial transmission path switching apparatus for concentrating a plurality of serial transmission paths with a plurality of transfer rates to one portion and selectively switching and connecting one of the serial transmission paths is used. This switching apparatus has, in the input and output sections, interface sections (equalizing sections using buffers) corresponding to the various transfer rates. The apparatus demodulates the waveform degradation of an input signal in the input section and switches the signal (signal switching). The waveform degradation in the signal selected by the switch section is demodulated by the output section and output to the output transmission path.
However, in such a conventional serial transmission path switching apparatus, the maximum number of channels for each transfer rate is predetermined, resulting in poor expandability. For example, this apparatus cannot flexibly cope with addition of serial transmission paths due to an increase in number of studios or equipment or addition of a serial transmission path with a new transfer rate.
More specifically, since the maximum number of lines for each transfer rate is predetermined, serial transmission paths with new transfer rates cannot be connected beyond the number of free lines of the matrix switch section. To solve this, the design of the interface configurations of the input and output sections must be changed, resulting in a large increase in cost.
Besides, in the conventional matrix switch section, a jitter is generated in the output signal due to a variation in delay in a processing circuit, and some influence of the band width of a passing frequency. To reduce this jitter and facilitate signal reconstruction at the receiving section, the matrix switch section has a re-timing section including a clock signal extraction circuit and a D-flip-flop (D-FF) circuit for each switch. The clock signal extraction circuit can cope with only a signal with a fixed transfer rate. To process signals having different transfer rates (multi-rate), switches dedicated for the respective signals must be provided.
In addition, conventionally, when a large-scale matrix switch section is to be formed to process both a low- and high-speed digital signals, the numbers of switches, distributors, and selectors or the circuit scale increases to result in an increase in the apparatus scale or power consumption.